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I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X
9-10
External Interrupt Control Register, Low Byte (EXTICONL)
F9H, Set 1, Bank 0, R/W
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
P1.3/INT3
EXTICONL bit configuration settings:
00
01
Enable interrupt by falling edge
Disable interrupt
10
11
Enable interrupt by both falling and rising edge
Enable interrupt by rising edge
P0.2/INT2 P0.1/INT1 P0.0/INT0
Figure 9-11. External Interrupt Control Register, Low Byte (EXTICONL)
External Interrupt Pending Register (EXTIPND)
F7H, Set 1, Bank 0, R/W
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
EXTIPND bit configuration settings:
0
1
Interrupt is pending (when read)
No interrupt pending (when read), clear pending bit (when write)
P0.2
(INT2)
P0.1
(INT1)
P0.0
(INT0)
P1.7
(INT7)
P1.6
(INT6)
P1.5
(INT5)
P1.4
(INT4)
P1.3
(INT3)
Figure 9-12. External Interrupt Pending Register (EXTIPND)