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HighWire HW400c/2 User Reference Guide Rev 1.0
3.2.6 MV64462 Ethernet Interface
The MV64462 contains an Ethernet MAC, which provides a MAC-to-MAC
connection to port 7 of the on-board Broadcom BMC5388 layer 2 Ethernet switch
(see Table 14). The connection is made via the RGMII ports on each device. The
operating speed of the RGMII port is 125 MHz.
3.2.7 MV64462 Device Interface
The Discovery III Device Interface connects the following functional elements:
• SRAM Device
• Boot PROM
• Disk-on-Chip
• CT Bus Controller
• CPLD
The device bus is a 32-bit interface with a default operating frequency of 100 MHz.
The following sections provide additional detail for each of the functional elements.
3.2.7.1 SRAM Device
The HW400c/2 includes a 512 KB SRAM device with a 32-bit wide data bus
necessary for the processor to boot. The device supports burst reads and writes.
3.2.7.2 Boot PROM
A 4 Mbit (512 KB) Boot PROM device is supported in a PLCC socket (XU4) that is
located underneath PTMC site B. The device allows for easy upgrade of boot and/or
diagnostic code. The socket also accepts most EPROM emulator cables. Burst
reads/writes to the boot ROM are not supported.
3.2.7.3 Disk-on-Chip
A Disk-on-Chip (DoC) flash file system device is used on the HW400c/2 for data
storage. DoC is a high-density flash device manufactured by M-Systems
Incorporated, with a data bus width of 16 bits. The 128 MB device is standard on the
HW400c/2, with the option of populating other devices for OEM configurations.
Burst reads/writes to the DoC are not possible due to the maximum input clock
frequency of the device (33 MHz) being slower than the 100 MHz device bus clock.
October 10, 2006 Copyright 2006, SBE, Inc. Page 22