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2. MCU
(1) Block diagram (MCU)
(2) CPU (HD6412351IF)
a. pin/signal table
Pin No. Pin name Signal name I/O Function Purpose Descriptions
1 /CS1 /CS1 OUT Area 1 chip select SRAM chip select L: Select
2 /CS0 /CS0 OUT Area 0 chip select Flash ROM chip select L: Select
3 VSS POW Ground pin
4 VSS POW Ground pin
5 VCC POW Power pin
6 A0 A0 OUT Address bus 0 System bus
7 A1 A1 OUT Address bus 1 System bus
8 A2 A2 OUT Address bus 2 System bus
9 A3 A3 OUT Address bus 3 System bus
10 VSS POW Ground pin
11 A4 A4 OUT Address bus 4 System bus
12 A5 A5 OUT Address bus 5 System bus
13 A6 A6 OUT Address bus 6 System bus
14 A7 A7 OUT Address bus 7 System bus
15 A8 A8 OUT Address bus 8 System bus
16 A9 A9 OUT Address bus 9 System bus
17 A10 A10 OUT Address bus 10 System bus
18 A11 A11 OUT Address bus 11 System bus
19 VSS POW Ground pin
20 A12 A12 OUT Address bus 12 System bus
21 A13 A13 OUT Address bus 13 System bus
(Pin descriptions) IN: Input pin OUT: Output pin BIDIR: Bi-directional pin ODN: Open drain output pin TR1: 3-state output pin POW: Power pin
AR-161
AR-160/161 FM/E [13] ELECTRICAL SECTION 12/1/1998
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