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APPLICATION NOTE 4.16
PRELIMINARY Rev. 1/13/94
HIGH PERFORMANCE EPP ETHERNET ADAPTER
USING THE PPC34C60 PPIC AND LAN91C92 SCECR
by Jeffrey C. Dunnihoo
DESIGN OVERVIEW:
The design described here showcases the high integration and simplicity of design with the LAN91C92
Single Chip Ethernet Controller and the PPC34C60 ECP/EPP Multi-Mode Parallel Port Peripheral Chip.
Both of these 100-pin PQFP ICs are mated to provide a very high performance Ethernet 10Base-T
adapter for the parallel port for use with laptops, embedded PCs, or temporary PC-network
connections.
The PPC34C60 PPIC regenerates standard ISA bus signals from the ECP/EPP data stream. This part
also supports daisy chaining up to 8 EPP devices and one standard parallel port device (such as a
printer) by adding J2 (See schematic.) The PPIC reassembles 4 and 8 bit EPP words into 8 and 16-bit
wide word transfers to the ISA bus for transfer rates 15 to 80 times that of a standard parallel port
interface. The PPIC also supports DMA transfers, but this is not required for the 91C92's PIO
interface.
The LAN91C92 SCECR contains 4.5K of buffer RAM, and a unique memory management unit which
eliminates much of the overhead that would otherwise need to be handled by the host over the EPP
interface. Configuration and Ethernet ID information is stored in a 4-pin serial EEPROM. The seven
programmable outputs of the PPIC allow full software configuration of the Ethernet controller. Two of
these outputs are used for power management functions.
The software drivers required for this design are identical to the LAN9000 series drivers required for
ISA designs. The only modification required is rerouting of direct I/O through EPP BIOS calls instead.
Ethernet interrupts will also be serviced through INT5 or 7, rather than INT10 or 11.
NOTE: This application note describes a paper design which has not been confirmed by a
hardware implementation. This application note should be used to convey the recommended
techniques for using the PPC34C60.