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Timer_B Operation
13-13Timer_B
Compare Latch TBCLx
The TBCCRx compare latch, TBCLx, holds the data for the comparison to the
timer value in compare mode. TBCLx is buffered by TBCCRx. The buffered
compare latch gives the user control over when a compare period updates.
The user cannot directly access TBCLx. Compare data is written to each
TBCCRx and automatically transferred to TBCLx. The timing of the transfer
from TBCCRx to TBCLx is user-selectable with the CLLDx bits as described
in Table 13−2.
Table 13−2.TBCLx Load Events
CLLDx Description
00 New data is transferred from TBCCRx to TBCLx immediately when
TBCCRx is written to.
01 New data is transferred from TBCCRx to TBCLx when TBR counts to 0
10 New data is transferred from TBCCRx to TBCLx when TBR counts to 0
for up and continuous modes. New data is transferred to from TBCCRx
to TBCLx when TBR counts to the old TBCL0 value or to 0 for up/down
mode
11
New data is transferred from TBCCRx to TBCLx when TBR
counts to the old TBCLx value.
Grouping Compare Latches
Multiple compare latches may be grouped together for simultaneous updates
with the TBCLGRPx bits. When using groups, the CLLDx bits of the lowest
numbered TBCCRx in the group determine the load event for each compare
latch of the group, except when TBCLGRP = 3, as shown in Table 13−3. The
CLLDx bits of the controlling TBCCRx must not be set to zero. When the
CLLDx bits of the controlling TBCCRx are set to zero, all compare latches
update immediately when their corresponding TBCCRx is written - no
compare latches are grouped.
Two conditions must exist for the compare latches to be loaded when grouped.
First, all TBCCRx registers of the group must be updated, even when new
TBCCRx data = old TBCCRx data. Second, the load event must occur.
Table 13−3.Compare Latch Operating Modes
TBCLGRPx Grouping Update Control
00 None Individual
01 TBCL1+TBCL2
TBCL3+TBCL4
TBCL5+TBCL6
TBCCR1
TBCCR3
TBCCR5
10 TBCL1+TBCL2+TBCL3
TBCL4+TBCL5+TBCL6
TBCCR1
TBCCR4
11
TBCL0+TBCL1+TBCL2+
TBCL3+TBCL4+TBCL5+TBCL6
TBCCR1