Filter
Top Products
DAC12 Operation
23-10 DAC12
23.2.7 DAC12 Interrupts
The DAC12 interrupt vector is shared with the DMA controller. Software must
check the DAC12IFG and DMAIFG flags to determine the source of the
interrupt.
The DAC12IFG bit is set when DAC12LSELx > 0 and DAC12 data is latched
from the DAC12_xDAT register into the data latch. When DAC12LSELx = 0,
the DAC12IFG flag is not set.
A set DAC12IFG bit indicates that the DAC12 is ready for new data. If both the
DAC12IE and GIE bits are set, the DAC12IFG generates an interrupt request.
The DAC12IFG flag is not reset automatically. It must be reset by software.