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2.13.1InitializingConfigurationRegisters
PeripheralArchitecture
Table14.DDR2SDRAMConfigurationbyMRSCommand
DDR2Memory
ControllerDDR2SDRAM
AddressBusValueRegisterBitDDR2SDRAMFieldFunctionSelection
DDR_A[12]012PowerDownExitFastexit
DDR_A[11:9]t_WR11:9WriteRecoveryWriterecoveryfromautoprecharge.Valueof2,
3,4,5,or6isprogrammedbasedonvalueof
theT_WRbitintheSDRAMtimingregister
(SDTIMR).
DDR_A[8]08DLLResetOutofreset
DDR_A[7]07Mode:TestorNormalNormalmode
DDR_A[6:4]CLbit6:4CASLatencyValueof2,3,4,or5isprogrammedbasedon
valueoftheCLbitintheSDRAMbank
configurationregister(SDBCR).
DDR_A[3]03BurstTypeSequential
DDR_A[2:0]3h2:0BurstLength8
Table15.DDR2SDRAMConfigurationbyEMRS(1)Command
DDR2Memory
ControllerDDR2SDRAM
AddressBusValueRegisterBitDDR2SDRAMFieldFunctionSelection
DDR_A[12]012OutputBufferEnableOutputbufferenable
DDR_A[11]011RDQSEnableRDQSdisable
DDR_A[10]110DQSenableDisablesdifferentialDQSsignaling.
DDR_A[9:7]09:7OCDCalibrationProgramExitOCDcalibration
DDR_A[6]06ODTValue(Rtt)Clearedto0toselect75ohms.Thisfeatureis
notsupportedbecausetheDDR_ODTsignalis
notpinnedout.
DDR_A[5:3]05:3AdditiveLatency0cyclesofadditivelatency
DDR_A[2]12ODTValue(Rtt)Setto1toselect75ohms.Thisfeatureisnot
supportedbecausetheDDR_ODTsignalisnot
pinnedout.
DDR_A[1]11OutputDriverImpedanceDDR2drivestrengthprogrammedtoweak
(60%).
DDR_A[0]00DLLenableDLLenable
PerformthefollowingstepswhenconfiguringtheDDR2memorycontrollermemory-mappedregisters:
1.ProgramtheDDRPHYcontrolregister(DDRPHYCR)bysettingthereadlatency(READLAT)bitsto
thedesiredvalueaswellasclearingtheDLLPWRDNbitto0.
2.ProgramtheSDRAMbankconfigurationregister(SDBCR)tothedesiredvaluewiththeTIMUNLOCK
bitsetto1(unlocked).
3.ProgramtheSDRAMtimingregister(SDTIMR)andSDRAMtimingregister2(SDTIMR2)tothe
desiredvaluestomeettheDDR2SDRAMmemorydatasheetspecification.
4.ProgramSDBCRtothedesiredvaluewiththeTIMUNLOCKbitclearedto0(locked).
5.ProgramtheRRbitintheSDRAMrefreshcontrolregister(SDRCR)tothedesiredvaluetomeetthe
refreshrequirementsoftheDDR2SDRAMmemory.
DDR2MemoryController 32SPRU986B–November2007
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