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2.7.3PossibleRaceCondition
2.8RefreshScheduling
PeripheralArchitecture
AraceconditionmayexistwhencertainmasterswritedatatotheDDR2memorycontroller.Forexample,
ifmasterApassesasoftwaremessageviaabufferinDDR2memoryanddoesnotwaitforindicationthat
thewritecompletes,whenmasterBattemptstoreadthesoftwaremessageitmayreadstaledataand
thereforereceiveanincorrectmessage.InordertoconfirmthatawritefrommasterAhaslandedbeforea
readfrommasterBisperformed,masterAmustwaitforthewritecompletionstatusfromtheDDR2
memorycontrollerbeforeindicatingtomasterBthatthedataisreadytoberead.IfmasterAdoesnot
waitforindicationthatawriteiscomplete,itmustperformthefollowingworkaround:
1.Performtherequiredwrite.
2.PerformadummywritetotheDDR2memorycontrollermoduleIDandrevisionregister.
3.PerformadummyreadtotheDDR2memorycontrollermoduleIDandrevisionregister.
4.IndicatetomasterBthatthedataisreadytobereadaftercompletionofthereadinstep3.The
completionofthereadinstep3ensuresthatthepreviouswritewasdone.
Foralistofthemasterperipheralsthatneedthisworkaround,seethedevice-specificdatasheet.
TheDDR2memorycontrollerissuesautorefresh(REFR)commandstoDDR2SDRAMdevicesatarate
definedintherefreshrate(REFRESH_RATE)bitfieldintheSDRAMrefreshcontrolregister(SDRFC).A
refreshintervalcounterisloadedwiththevalueoftheREFRESH_RATEbitfieldanddecrementsby1
eachcycleuntilitreacheszero.Oncetheintervalcounterreacheszero,itreloadswiththevalueofthe
REFRESH_RATEbit.Eachtimetheintervalcounterexpires,arefreshbacklogcounterincrementsby1.
Conversely,eachtimetheDDR2memorycontrollerperformsaREFRcommand,thebacklogcounter
decrementsby1.ThismeanstherefreshbacklogcounterrecordsthenumberofREFRcommandsthe
DDR2memorycontrollercurrentlyhasoutstanding.
TheDDR2memorycontrollerissuesREFRcommandsbasedonthelevelofurgency.Thelevelof
urgencyisdefinedinTable7.Whenevertherefreshlevelofurgencyisreached,theDDR2memory
controllerissuesaREFRcommandbeforeservicinganynewmemoryaccessrequests.FollowingaREFR
command,theDDR2memorycontrollerwaitsT_RFCcycles,definedintheSDRAMtiming1register
(SDTIM1),beforerecheckingtherefreshurgencylevel.
Inadditiontotherefreshcounterpreviouslymentioned,aseparatebacklogcounterensurestheinterval
betweentwoREFRcommandsdoesnotexceed8×therefreshrate.Thisbacklogcounterincrementsby1
eachtimetheintervalcounterexpiresandresetstozerowhentheDDR2memorycontrollerissuesa
REFRcommand.Whenthisbacklogcounterisgreaterthan7,theDDR2memorycontrollerissuesfour
REFRcommandsbeforeservicinganynewmemoryrequests.
TherefreshcountersdonotoperatewhentheDDR2memoryisinself-refreshmode.
Table7.RefreshUrgencyLevels
UrgencyLevelDescription
RefreshMayBacklogcountisgreaterthan0.IndicatesthereisabacklogofREFRcommands,whentheDDR2memory
controllerisnotbusyitwillissuetheREFRcommand.
RefreshReleaseBacklogcountisgreaterthan3.IndicatesthelevelatwhichenoughREFRcommandshavebeenperformed
andtheDDR2memorycontrollermayservicenewmemoryaccessrequests.
RefreshNeedBacklogcountisgreaterthan7.IndicatestheDDR2memorycontrollershouldraisetheprioritylevelofa
REFRcommandaboveservicinganewmemoryaccess.
RefreshMustBacklogcountisgreaterthan11.IndicatesthelevelatwhichtheDDR2memorycontrollershouldperforma
REFRcommandbeforeservicingnewmemoryaccessrequests.
SPRUEK5A–October2007DSPDDR2MemoryController25
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