Filter
Top Products
TMP92CZ26A
92CZ26A-484
(d) <CEN>
Select enable/disable of the pin for SD card or MMC.
When the card isn’t inserted or no-power supply to DVcc, penetrated current is flowed
because SPDI pin becomes floating. In addition, current is flowed to the card
because
SPCS
, SPCLK and SPDO pin output “1”. This register can avoid these matters.
If write <CEN> to “0” with PRCR and PRFC selecting
SPCS , SPCLK, SPDO and SPDI
signal, SPDI pin is prohibited to input (avoiding penetrated current) and
SPCS , SPCLK,
SPDO pin become high impedance.
Please write <CEN>=“1” after card is inserted, supply power to Vcc of card and supply
clock to this circuit (SPIMD<XEN>=“1”).
(e) <SPCS_B>
Set the value that outputs to
SPCS pin.
(f) <UNIT16>
Select the length of transmit/receive data. Data length is described as UNIT downward.
Please don't change the setting of this register when transmitting/receiving is in
operation.
(g) <FDPXE>
Select whether using alignment function for transmit/receive per UNIT during full
duplex.
Please don't change the setting of this register when transmitting/receiving is in
operation.
(h)<TXMOD>
Select UNIT/Sequential transmission. During transmission, it is prohibited to change
the transmission mode; Sequential
→UNIT, UNIT → Sequential.
For UNIT transmit, the data in transmit FIFO is invalid. TEMP interrupt generates
when the data is shifted from transmit data register (SPITD) to transmit buffer.
For sequential transmit, 32 bytes of the data in FIFO is valid. TEMP interrupt
generates when the space of the FIFO becomes 16 bytes size and 32 bytes.
(i)<TXE>
Set enable/disable of transmit. Transmission starts when set to “1”after writing
transmit data to transmit FIFO or set to “1” before writing transmit data to transmit
FIFO. During transmission, it is possible to change enable/disable. If cleared to “0” during
transmission, transmission is stopped after finishing transmitting the UNIT data in
transmitting.
(j)<RXMOD>
Select UNIT/Sequential receives. During receiving, it is prohibited to change receiving
mode; Sequential
→UNIT, UNIT → Sequential
In UNIT receive mode, receive FIFO is invalid and RFUL interrupt generates when the
received data is shifted from receive buffer to receive data register (SPIRD).
In sequential receive mode, receive FIFO is valid and RFUL interrupt generates when
16 and 32 bytes of the data is loaded to the FIFO.