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Appendix A Programming the Watchdog Timer ........ 19
A.1 Programming the watchdog timer ............................... 20
Appendix B System Assignments.............................. 23
B.1 System I/O ports ............................................................ 24
B.2 DMA channel assignments........................................... 25
B.3 Interrupt assignments ................................................... 26
B.4 1st MB memory map ..................................................... 27
Appendix C LVDS Connection ................................... 29
C.1 LVDS Introduction ......................................................... 30
C.2 LVDS Pin assingments .................................................. 31