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23614K—October 2003 AMD Athlon™ Processor Model 4 Revision Guide
Preliminary Information
17 Code Modifications that Coincide with Level 2 Instruction TLB Translations May Escape
Detection Resulting in Stale Code Execution
Products Affected. A4, A5, A6, A7, A9
Normal Specified Operation. Self-modifying code sequences should be correctly detected and handled in a
manner that results in correct canonical results; stale code should not be executed.
Non-conformance. If the following events occur within a single clock cycle and the pipeline is not flushed
by a coincidental event, then the processor will execute the stale code once instead of the newly
generated code.
1. A write operation corresponding to the code self-modification has generated an instruction
cache invalidation
2. The processor is fetching the line that is being invalidated
3. The fetch misses in the Level 1 instruction TLB
4. The fetch hits in the Level 2 instruction TLB
In this scenario the processor will properly invalidate the instruction cache line but will not mark the
appropriate bit within the instruction buffer used to track instructions within the pipeline. This causes
the pipeline to not be flushed and leads to execution of invalid instructions. Subsequent attempts to
execute the overwritten instruction will miss in the instruction cache and the correct instruction data
will be fetched from the L2 and subsequently executed.
Potential Effect on System. Stale code will be executed resulting in unpredictable system behavior.
Suggested Workaround. Consult with your platform vendor for a BIOS that works around this erratum.
Resolution Status. No fix planned.