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Condition Register
This special 32-bit register summarizes the states of the floating-point and integer units.
The condition register also indicates the results of comparison operations and provides
a means for testing them as branch conditions. By bridging information between the
branch unit and other functional units, the condition register improves the flow of data
throughout the execution core.
Three-Component Branch Prediction Logic
Advanced processors use branch prediction and speculative operation to increase
efficiency. A branch is a question in the processing queue: Which instruction should
go next? Branch prediction anticipates the answer; and speculative operation causes
that instruction to be executed. If the prediction is correct, the processor works more
efficiently—since the speculative operation has executed an instruction before it’s
required. If the prediction is incorrect, the processor must clear the unneeded branch,
as well as any related data and instructions, resulting in an empty space called a pipeline
bubble. Pipeline bubbles reduce performance as the processor marks time waiting for
the next instruction.
The PowerPC G5 features an innovative three-component branch prediction logic
to reduce pipeline bubbles and maximize processor efficiency. The success or failure
of each prediction is captured in three 16K branch history tables—local, global, and
selector—that are used to improve the accuracy of future branch predictions.
Local branch prediction takes place as individual instructions are fetched into the pro-
cessor and the types of branches are recorded in the local branch history table. Global
branch prediction occurs at the same time: Branches are identified in their processing
context, relating to preceding and subsequent operations; and the results are recorded
in the global branch history table. The third,“selector” history table identifies which
prediction type, local or global, was more accurate in predicting the outcome of each
branch. This dynamic local/global/selector branch history scheme can predict branch
processes with a high degree of accuracy, allowing the PowerPC G5 to efficiently use
every processing cycle.
State-of-the-Art Process Technology from IBM
The PowerPC G5 is fabricated in one of IBM’s world-class semiconductor manufacturing
facilities. With industry-leading build, assembly, and test technology, IBM uses a cutting-
edge 130-nanometer process with more than 58 million silicon-on-insulator (SOI) trans-
istors and eight layers of copper interconnects.
SOI refers to the placement of a thin layer of insulator between transistors and bulk
silicon. When transistors are built on this SOI layer, their capacitance, or the tendency
to store an electrical charge, is reduced—resulting in faster operation.
For further performance gains, an additive-copper wiring process replaces the con-
ventional subtractive-aluminum process. As semiconductor wires are made thinner
and narrower, aluminum resists the flow of electricity and slows down transmission
of electrical signals. Copper wiring is less resistant and results in a 40 percent gain in
conductivity, again for faster processor operation.
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White Paper
PowerPC G5
Copper interconnects improve conductivity
and boost processor performance.
IBM is a worldwide leader in processor
fabrication technologies, with a new
$3 billion, state-of-the-art facility in
East Fishkill, New York.