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ASUS A7M266 User’s Manual64
4. BIOS SETUP
4. BIOS SETUP
Chip Configuration
AGP Drive Strength P Ctrl [C]
(When AGP 4X Drive Strength set to [Manual])
Configuration options: [0] [1] [2]...[F]
AGP Drive Strenght N Ctrl [5]
(When AGP 4X Drive Strength set to [Manual])
Configuration options: [0] [1] [2]...[F]
AGP Data Strobe P Ctrl [F]
(When AGP 4X Drive Strength set to [Manual])
Configuration options: [0] [1] [2]...[F]
AGP Data Strobe N Ctrl [F]
(When AGP 4X Drive Strength set to [Manual])
Configuration options: [0] [1] [2]...[F]
SDRAM Configuration [By SPD]
This sets the optimal timings for SDRAM related fields, depending on the
memory modules that you are using. Default setting is [By SPD], which
configures the subsequent 3 items by reading the contents in the SPD (Se-
rial Presence Detect) device. The EEPROM on the memory module stores
critical parameter information about the module, such as memory type, size,
speed, voltage interface, and module banks. Configuration options: [By
SPD][User Define]
SDRAM CAS Latency
This controls the latency between the SDRAM read command and the time
that the data actually becomes available. NOTE: This field will only be ad-
justable when SDRAM Configuration is set to [User Define].
SDRAM RAS Precharge Time
This controls the idle clocks after issuing a precharge command to the
SDRAM. NOTE: This field will only be adjustable when SDRAM Con-
figuration is set to [User Define].
SDRAM RAS to CAS Delay
This controls the latency between the SDRAM active command and the
read/write command. NOTE: This field will only be adjustable when
SDRAM Configuration is set to [User Define].
Delayed Transaction [Disabled]
Leave on default setting. [Enabled] frees the PCI Bus when the CPU is
accessing 8-bit ISA devices that normally consume about 50-60 PCI Clocks
without PCI delayed transaction. Select [Disabled] for ISA devices that are
not PCI 2.1 compliant. Configuration options: [Disabled] [Enabled]
PCI to DRAM Prefetch [Enabled]
Configuration options: [Disabled] [Enabled]