AMI
AST
Award
controller input buffer to be free. Calculating ROM BIOS checksum.. Video disabled and sys-
tem timer test begin Video disabled and system timer counting
OK.
(06)Support chipset initialize.
(06)Test memory refresh toggle; RAM must be periodically refreshed in-order to
keep the memory from decaying. This function assures that the memory refresh
function is working properly. Initialize chips.
Appendix A
(06)ROM is enabled. Calculating ROM BIOS checksum, and waiting for Keyboard
Chips & Tech (06)64K RAM Failed.
alize system hardware (Beep)=1
3.DMA page register write/read test
in-progress or fail.
AMI
Award
(07)ROM BIOS checksum passed. CMOS shutdown register test to be done
next.ROM BIOS checksum passed, Keyboard controller I/B free. Going to issue the
BAT command to keyboard controller. Going to issue the BAT command to keyboard
controller.CH-2 of 8254 initialization half way.CH-2 of 8253 test OK
(07)Verifies CMOS's basis R/W functionality Test CMOS interface and battery
status; Verifies CMOS is working correctly, detects bad battery. Setup low memory;
Early chip set initialization; Memory presence test; OEM chip set routines; Clear
low 64K of memory; Test first 64K memory; clear lower 256K of memory, enable
parity checking and test parity in lower 256K; test lower 25 If the BIOS detects
error 2C,2E,or 30(base 512K RAM error),it displays 6K memory. Set up stack,beep.
Read/write/verify CPU registers.
Chips & Tech (07)64K RAM failed data test (Base Memory)
ACER (08)Shutdown 0.
AMI
Award
(08)CMOS shutdown register test done. CMOS checksum calculation to be done
next. BAT command to keyboard controller is issued. Going to verify the BAT command.
Going to verify the BAT command. CH-2 of timer initialization over.
CH-2 delta count test OK
(08)Setup low memory; Early chip set initialization; Memory presence test; OEM
chip set routines; Clear low 64K of memory; Test first 64K memory; clear lower
256K of memory, enable parity checking and test parity in lower 256K; test lower
256K memory. Set up stack, beep. Setup interrupt vector table in lower 1K RAM
area; Initialize first 120 interrupt vectors with SPURIOUS_INT_HDLR and initialize INT 00h-
1Fh according to INT_TBL. Initialize CMOS timer.
Chips & Tech (08)Interrupt Controller bad.
Phoenix&Dell (08)Initialize chipset registers with POST values. [Beep]= 1-3-1 RAM refresh
AMI
AST
(09)CMOS checksum calculation is done, CMOS diag byte written. CMOS initialize to begin.
Keyboard controller BAT result verified. Keyboard command
byte to be written next.(09)Keyboard command byte to be written next. CH-1 of
timer initialization over. CH-1 delta count test OK.
(09)Verify BIOS ROM checksum, flush external cache.
(09)Program the configuration register of Cyrix CPU. OEM specific cache initialization., Early
Cache initialization; Cyrix CPU initialization; cache initialization. Test CMOS RAM
checksum; beep; also test extended storage of parameters in the motherboard chipset; if not
warm- booting; display the Test
CMOS RAM checksum message, if bad, or insert key pressed, load defaults if bad.
Chips & Tech (09)Unexpected interrupt is occurring.
Phoenix&Dell (09)Set POST flay.(Beep)=1
AMI
Award
(0A)CMOS initialization done(if any). Keyboard command byte code is issued.
Going to write command byte data. Go- ing to write command byte data. CH-0 of
timer initialization over. CH-0 delta count test OK
(0A)Initialize the first 32 interrupt vectors. Initialize INTs 33 to 120.Early Power Management
initialization. Setup interrupt vector table in lower 1K RAM area; Initialize first 120 interrupt
vectors with SPURIOUS_INT_HDLR and initialize
INT 00h-1Fh according to INT_TBL. Initialize key- board; Detect type of keyboard
controller(optional 8242 or 8248, with Nedadon XOR gate control); Set NUM_LOCK status.
Reset keyboard test keyboard controller interface to verify it
returned AAH and responded to enable/disable commands, set keyboard buffer,
enable keyboard and keyboard interrupts for normal use, beep, halt .Initialize Video
Chips & Tech (0A)Timer cannot interrupt.
6
