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CY62157EV18 MoBL
®
Document #: 38-05490 Rev. *D Page 5 of 12
Switching Characteristics (Over the Operating Range)
[11,
12
]
Parameter Description
55 ns
Unit
Min Max
Read Cycle
t
RC
Read Cycle Time 55 ns
t
AA
Address to Data Valid 55 ns
t
OHA
Data Hold from Address Change 10 ns
t
ACE
CE
1
LOW and CE
2
HIGH to Data Valid 55 ns
t
DOE
OE LOW to Data Valid 25 ns
t
LZOE
OE LOW to Low-Z
[13]
5ns
t
HZOE
OE HIGH to High-Z
[13, 14]
18 ns
t
LZCE
CE
1
LOW and CE
2
HIGH to Low-Z
[13]
10 ns
t
HZCE
CE
1
HIGH and CE
2
LOW to High-Z
[13, 14]
18 ns
t
PU
CE
1
LOW and CE
2
HIGH to Power Up 0 ns
t
PD
CE
1
HIGH and CE
2
LOW to Power Down 55 ns
t
DBE
BLE/BHE LOW to Data Valid 55 ns
t
LZBE
[15]
BLE/BHE LOW to Low-Z
[13]
10 ns
t
HZBE
BLE/BHE HIGH to High-Z
[13, 14]
18 ns
Write Cycle
[16]
t
WC
Write Cycle Time 45 ns
t
SCE
CE
1
LOW and CE
2
HIGH
to Write End 35 ns
t
AW
Address Setup to Write End 35 ns
t
HA
Address Hold from Write End 0 ns
t
SA
Address Setup to Write Start 0 ns
t
PWE
WE Pulse Width 35 ns
t
BW
BLE/BHE LOW to Write End 35 ns
t
SD
Data Setup to Write End 25 ns
t
HD
Data Hold from Write End 0 ns
t
HZWE
WE LOW to High-Z
[13, 14]
18
ns
t
LZWE
WE HIGH to Low-Z
[13]
10 ns
Notes
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1V/ns or less, timing reference levels of V
CC(typ)
/2, input pulse
levels of 0 to V
CC(typ)
, and output loading of the specified I
OL
/I
OH
as shown in the “AC Test Loads and Waveforms” on page 4.
12.AC timing parameters are subject to byte enable signals (BHE
or BLE) not switching when chip is disabled. Please see application note AN13842 for furthe
r
clarification.
13.At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any
given device.
14.t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the output enters a high impedance state.
15.If both byte enables are toggled together, this value is 10 ns.
16.The internal write time of the memory is defined by the overlap of WE
, CE
= V
IL
, BHE and/or BLE = V
IL
, and CE
2
= V
IH
. All signals must be ACTIVE to initiate a
write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that
terminates the write.
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