Filter
Top Products
CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Document #: 38-06078 Rev. *B Page 11 of 18
Notes
29.CE
= HIGH for the duration of the above timing (both write and read cycle).
30.I/O
0R
= I/O
0L
= LOW (request semaphore); CE
R
= CE
L
= HIGH.
31.Semaphores are reset (available to both ports) at cycle start.
32.If t
SPS
is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable.
Switching Waveforms
(continued)
t
SOP
t
SAA
VALID ADRESS VALID ADRESS
t
HD
DATA
IN
VALID
DATA
OUT
VALID
t
OHA
t
AW
t
HA
t
ACE
t
SOP
t
SCE
t
SD
t
SA
t
PWE
t
SWRD
t
DOE
WRITE CYCLE READ CYCLE
OE
R/W
I/O
0
SEM
0
–A
2
Figure 9. Semaphore Read After Write Timing, Either Side
[29]
A
MATCH
t
SPS
A
0L
–A
2L
MATCH
R/W
L
SEM
L
A
0R
–A
2R
R/W
R
SEM
R
Figure 10. Timing Diagram of Semaphore Contention
[30, 31, 32]
[+] Feedback