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CY7C1141V18, CY7C1156V18
CY7C1143V18, CY7C1145V18
Document Number: 001-06583 Rev. *D Page 24 of 28
Switching Waveforms
Read/Write/Deselect Sequence
Figure 7. Waveform for 2.0 Cycle Read Latency
[30, 31, 32]
t
KH
t
KL
t
CYC
t
KHKH
NOPREAD
NOP
WRITE READ
WRITE
1
23 45 6
7
8
t
t
t
t
SA
HA
SC HC
t
HD
t
SC
t
HC
A0
A1
A2
A3
t
t
SD
HD
t
SD
D11D10
D12 D13 D30 D31
D32 D33
D
A
WPS
RPS
K
K
DON’T CARE UNDEFINED
CQ
CQ
t
CQOH
CCQO
t
t
CQOH
CCQO
t
t
QVLD
QVLD
t
QVLD
(Read Latency = 2.0 Cycles)
CLZ
t
t
CO
t
DOH
t
CQDOH
CQD
t
t
CHZ
Q00
Q01
Q20
Q02
Q21
Q03
Q22
Q23
t
CQH
t
CQHCQH
Q
Notes
30.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.
31.Outputs are disabled (High-Z) one clock cycle after a NOP.
32.In this example, if address A2 = A1, then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.
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