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CY7C1215H
Document #: 38-05666 Rev. *B Page 5 of 15
Interleaved Burst Address Table
(MODE = Floating or V
DD
)
First
Address
A
1
, A
0
Second
Address
A
1
, A
0
Third
Address
A
1
, A
0
Fourth
Address
A
1
, A
0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Linear Burst Address Table
(MODE = GND)
First
Address
A
1
, A
0
Second
Address
A
1
, A
0
Third
Address
A
1
, A
0
Fourth
Address
A
1
, A
0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min. Max. Unit
I
DDZZ
Sleep mode standby current ZZ > V
DD
– 0.2V 40 mA
t
ZZS
Device operation to ZZ ZZ > V
DD
– 0.2V 2t
CYC
ns
t
ZZREC
ZZ recovery time ZZ < 0.2V 2t
CYC
ns
t
ZZI
ZZ Active to sleep current This parameter is sampled 2t
CYC
ns
t
RZZI
ZZ Inactive to exit sleep current This parameter is sampled 0 ns
Truth Table
[2, 3, 4, 5, 6]
Next Cycle Add. Used ZZ CE
1
CE
2
CE
3
ADSP ADSC ADV OE DQ Write
Unselected None L H X X X L X X Tri-State X
Unselected None L L X H L X X X Tri-State X
Unselected None L L L X L X X X Tri-State X
Unselected None L L X H H L X X Tri-State X
Unselected None L L L X H L X X Tri-State X
Begin Read External L L H L L X X X Tri-State X
Begin Read External L L H L H L X X Tri-State Read
Continue Read Next L X X X H H L H Tri-State Read
Continue Read Next L X X X H H L L DQ Read
Continue Read Next L H X X X H L H Tri-State Read
Continue Read Next L H X X X H L L DQ Read
Suspend Read Current L X X X H H H H Tri-State Read
Suspend Read Current L X X X H H H L DQ Read
Suspend Read Current L H X X X H H H Tri-State Read
Suspend Read Current L H X X X H H L DQ Read
Begin Write Current L X X X H H H X Tri-State Write
Begin Write Current L H X X X H H X Tri-State Write
Begin Write External L L H L H H X X Tri-State Write
Continue Write Next L X X X H H H X Tri-State Write
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write Enable signals (BW
A
,BW
B
,BW
C
,BW
D
) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals
(BW
A
,BW
B
,BW
C
,BW
D
), BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE
signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a Read cycle when ADSP
is asserted, regardless of the state of GW, BWE, or BW
[A:D]
. Writes may occur only on subsequent clocks
after the ADSP
or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to Tri-State. OE is a
don't care for the remainder of the Write cycle
6. OE
is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Tri-State when OE
is inactive or when the device is deselected, and all data bits behave as output when OE
is active (LOW).
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