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CY7C1266V18, CY7C1277V18
CY7C1268V18, CY7C1270V18
Document Number: 001-06347 Rev. *D Page 23 of 27
Switching Waveforms
Read/Write/Deselect Sequence
[29, 30]
Figure 5. Waveform for 2.5 Cycle Read Latency
1
2
3
4
5
6
7
89
10
READ
READ
NOP WRITEWRITE
t
NOP
11
LD
R/W
A
t
KH
t
KL
t
CYC
t
HC
t
SA
t
HA
DON’T CARE
UNDEFINED
SC
A0
A1
A2
A3
A4
CQ
CQ
K
QVLD
t
NOP
NOP
DQ
K
t
CCQO
t
CQOH
t
CCQO
t
CQOH
QVLD
t
QVLD
t
QVLD
t
KHKH
12
READ
(Read Latency = 2.5 Cycles)
NOP
NOP
t
CLZ
t
CHZ
CQDOH
Q00
Q11
Q01
Q10
t
DOH
t
CO
Q40
t
SD
HD
t
SD
t
HD
D20
D21
D30 D31
t
t
CQD
t
t
CQH
t
CQHCQH
Notes
29.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.
30.Outputs are disabled (High-Z) one clock cycle after a NOP.
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