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CY7C1316JV18, CY7C1916JV18
CY7C1318JV18, CY7C1320JV18
Document Number: 001-15271 Rev. *B Page 3 of 26
Logic Block Diagram (CY7C1318JV18)
Logic Block Diagram (CY7C1320JV18)
Write
Reg
Write
Reg
CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. Decode
Read Data Reg.
R/W
DQ
[17:0]
Output
Logic
Reg.
Reg.
Reg.
18
18
36
18
BWS
[1:0]
V
REF
Write Add. Decode
18
20
C
C
18
LD
Control
Burst
Logic
A0
A
(19:1)
CQ
CQ
R/W
DOFF
512K x 18 Array
512K x 18 Array
19
18
Write
Reg
Write
Reg
CLK
A
(18:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. Decode
Read Data Reg.
R/W
DQ
[35:0]
Output
Logic
Reg.
Reg.
Reg.
36
36
72
36
BWS
[3:0]
V
REF
Write Add. Decode
36
19
C
C
36
LD
Control
Burst
Logic
A0
A
(18:1)
CQ
CQ
R/W
DOFF
256K x 36 Array
256K x 36 Array
18
36
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