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CY7C1316JV18, CY7C1916JV18
CY7C1318JV18, CY7C1320JV18
Document Number: 001-15271 Rev. *B Page 2 of 26
Logic Block Diagram (CY7C1316JV18)
Logic Block Diagram (CY7C1916JV18)
Write
Reg
Write
Reg
CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. Decode
Read Data Reg.
R/W
DQ
[7:0]
Output
Logic
Reg.
Reg.
Reg.
8
8
16
8
NWS
[1:0]
V
REF
Write Add. Decode
8
20
C
C
8
LD
Control
CQ
CQ
R/W
DOFF
1M x 8 Array
1M x 8 Array
8
Write
Reg
Write
Reg
CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. Decode
Read Data Reg.
R/W
DQ
[8:0]
Output
Logic
Reg.
Reg.
Reg.
9
9
18
9
BWS
[0]
V
REF
Write Add. Decode
9
20
C
C
9
LD
Control
CQ
CQ
R/W
DOFF
1M x 9 Array
1M x 9 Array
9
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