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PRELIMINARY
2-Mbit (64K x 32) Flow-Through SRAM
with NoBL™ Architecture
CY7C1333H
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 001-00209 Rev. ** Revised April 11, 2005
Features
• Can support up to 133-MHz bus operations with zero
wait states.
— Data is transferred on every clock.
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use
OE
• Registered inputs for flow-through operation
• Byte Write capability
• 64K x 32 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
— 8.0 ns (for 100-MHz device)
• Clock Enable (CEN
) pin to suspend operation
• Synchronous self-timed writes Offered in Lead-Free
• Asynchronous Output Enable
• Offered in Lead-Free JEDEC-standard 100 TQFP
package
• Burst Capability—linear or interleaved burst order
• Low standby power
Functional Description
[1]
The CY7C1333H is a 3.3V, 64K x 32 Synchronous
Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1333H is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to
enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN
) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two Byte Write Select
(BW
[A:D]
) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE
) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
C
MODE
BW
A
BW
B
WE
CE1
CE2
CE3
OE
READ LOGIC
DQ
s
MEMORY
ARRAY
E
INPUT
REGISTER
BW
C
BW
D
ADDRESS
REGISTER
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
ADV/LD
CE
ADV/LD
C
C
LK
C
EN
WRITE
DRIVERS
D
A
T
A
S
T
E
E
R
I
N
G
S
E
N
S
E
A
M
P
S
WRITE ADDRESS
REGISTER
A0, A1, A
O
U
T
P
U
T
B
U
F
F
E
R
S
E
ZZ
SLEEP
Control
Logic Block Diagram
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