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PRELIMINARY
CY7C1333H
Document #: 001-00209 Rev. ** Page 7 of 12
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VDD Relative to GND ...... –0.5V to +4.6V
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to V
DDQ
+ 0.5V
DC Input Voltage....................................–0.5V to V
DD
+ 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Ambient
Temperature (T
A
)V
DD
V
DDQ
Com’l 0°C to +70°C 3.3V – 5%/+10% 3.3V – 5% to
V
DD
Ind’l -40°C to +85°C
Electrical Characteristics Over the Operating Range
[9,10]
Parameter Description Test Conditions Min. Max. Unit
V
DD
Power Supply Voltage 3.135 3.6 V
V
DDQ
I/O Supply Voltage for 3.3V I/O 3.135 V
DD
V
V
OH
Output HIGH Voltage for 3.3V I/O, I
OH
= –4.0 mA 2.4 V
V
OL
Output LOW Voltage for 3.3V I/O, I
OL
= 8.0 mA 0.4 V
V
IH
Input HIGH Voltage for 3.3V I/O 2.0 V
DD
+ 0.3V V
V
IL
Input LOW Voltage
[9]
for 3.3V I/O –0.3 0.8 V
I
X
Input Load Current (except
ZZ and MODE)
GND ≤ V
I
≤ V
DDQ
–5 5 µA
Input Current of MODE Input = V
SS
–30 µA
Input = V
DD
5 µA
Input Current of ZZ Input = V
SS
–5 µA
Input = V
DD
30 µA
I
OZ
Output Leakage Current GND ≤ V
I
≤ V
DD
, Output Disabled –5 5 µA
I
DD
V
DD
Operating Supply
Current
V
DD
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
CYC
7.5-ns cycle, 133 MHz 225 mA
10-ns cycle, 100 MHz 205 mA
I
SB1
Automatic CE Power-down
Current—TTL Inputs
V
DD
= Max, Device Deselected,
V
IN
≥ V
IH
or V
IN
≤ V
IL
, f = f
MAX
,
inputs switching
7.5-ns cycle, 133 MHz 90 mA
10-ns cycle, 100 MHz 80 mA
I
SB2
Automatic CE Power-down
Current—CMOS Inputs
V
DD
= Max, Device Deselected,
V
IN
≥ V
DD
– 0.3V or V
IN
≤ 0.3V,
f = 0, inputs static
All speeds 40 mA
I
SB3
Automatic CE Power-down
Current—CMOS Inputs
V
DD
= Max, Device Deselected,
V
IN
≥ V
DDQ
– 0.3V or V
IN
≤ 0.3V,
f = f
MAX
, inputs switching
7.5-ns cycle, 133 MHz 75 mA
10-ns cycle, 100 MHz 65 mA
I
SB4
Automatic CE Power-down
Current—TTL Inputs
V
DD
= Max, Device Deselected,
V
IN
≥ V
DD
– 0.3V or V
IN
≤ 0.3V,
f = 0, inputs static
All speeds 45 mA
Thermal Resistance
[11]
Parameters Description Test Conditions
100 TQFP
Package Unit
Θ
JA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA/JESD51
30.32 °C/W
Θ
JC
Thermal Resistance
(Junction to Case)
6.85 °C/W
Notes:
9. Overshoot: V
IH
(AC) < V
DD
+1.5V (Pulse width less than t
CYC
/2), undershoot: V
IL
(AC)> –2V (Pulse width less than t
CYC
/2).
10.Power-up: Assumes a linear ramp from 0V to V
DD
(min.) within 200 ms. During this time V
IH
< V
DD
and V
DDQ
< V
DD
.
11. Tested initially and after any design or process changes that may affect these parameters.
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