Filter
Top Products
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
Document #: 38-05544 Rev. *F Page 23 of 29
Read/Write Cycle Timing
[26, 28, 29]
Timing Diagrams (continued)
t
CYC
t
CL
CLK
t
ADH
t
ADS
ADDRESS
t
CH
t
AH
t
AS
A2
t
CEH
t
CES
Single WRITE
D(A3)
A3 A4
BURST READ
Back-to-Back READs
High-Z
Q(A2)
Q(A4) Q(A4+1)
Q(A4+2)
Q(A4+3)
t
WEH
t
WES
t
OEHZ
t
DH
t
DS
t
CDV
t
OELZ
A1 A5 A6
D(A5) D(A6)
Q(A1)
Back-to-Back
WRITEs
DON’T CARE UNDEFINED
ADSP
ADSC
BWE, BW
X
CE
ADV
OE
Data In (D)
Data Out (Q)
Notes:
28.The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP
or ADSC.
29.
GW
is HIGH.
[+] Feedback