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Document #: 001-07162 Rev. *C Revised May 22, 2008 Page 30 of 30
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document
are the trademarks of their respective holders.
CY7C1392CV18, CY7C1992CV18
CY7C1393CV18, CY7C1394CV18
© Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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Document History Page
Document Title: CY7C1392CV18/CY7C1992CV18/CY7C1393CV18/CY7C1394CV18, 18-Mbit DDR-II SIO SRAM 2-Word
Burst Architecture
Document Number: 001-07162
Rev. ECN No.
Submission
Date
Orig. of
Change
Description of Change
** 433284 See ECN NXR New data sheet
*A 462615 See ECN NXR Changed t
CYC
from 100 ns to 50 ns, changed t
TH
and t
TL
from 40 ns to 20 ns, changed
t
TMSS
, t
TDIS
, t
CS
, t
TMSH
, t
TDIH
, t
CH
from
10 ns to 5 ns and changed t
TDOV
from 20 ns
to 10 ns in TAP AC Switching Characteristics table
Modified Power-Up waveform
*B 1523386 See ECN VKN/AESA Converted from preliminary to final, Updated Logic Block diagram, Updated I
DD
/I
SB
specs, Changed DLL minimum operating frequency from 80MHz to 120MHz, Changed
t
CYC
max spec to 8.4ns for all speed bins, Modified footnotes 20 and 28.
*C 2507766 05/23/08 VKN/PYRS Changed Ambient Temperature with Power Applied from “–10°C to +85°C” to “–55°C
to +125°C” in the “Maximum Ratings“ on page 20, Updated power up sequence
waveform and its description, Added footnote #19 related to I
DD
,
Changed Θ
JA
spec
from 28.51 to 18.7, Changed Θ
JC
spec from 5.91 to 4.5, Changed JTAG ID [31:29]
from 001 to 000.
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