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CY7C1399B
Document #: 38-05071 Rev. *A Page 4 of 10
Switching Characteristics Over the Operating Range
[5]
1399B–10 1399B–12
Parameter Description Min. Max. Min. Max. Unit
READ CYCLE
t
RC
Read Cycle Time 10 12 ns
t
AA
Address to Data Valid 10 12 ns
t
OHA
Data Hold from Address Change 3 3 ns
t
ACE
CE LOW to Data Valid 10 12 ns
t
DOE
OE LOW to Data Valid 5 5 ns
t
LZOE
OE LOW to Low Z
[6]
00ns
t
HZOE
OE HIGH to High Z
[6, 7]
55ns
t
LZCE
CE LOW to Low Z
[6]
33ns
t
HZCE
CE HIGH to High Z
[6, 7]
56ns
t
PU
CE LOW to Power-Up 0 0 ns
t
PD
CE HIGH to Power-Down 10 12 ns
WRITE CYCLE
[8, 9]
t
WC
Write Cycle Time 10 12 ns
t
SCE
CE LOW to Write End 8 8 ns
t
AW
Address Set-Up to Write End 7 8 ns
t
HA
Address Hold from Write End 0 0 ns
t
SA
Address Set-Up to Write Start 0 0 ns
t
PWE
WE Pulse Width 7 8 ns
t
SD
Data Set-Up to Write End 5 7 ns
t
HD
Data Hold from Write End 0 0 ns
t
HZWE
WE LOW to High Z
[8]
77ns
t
LZWE
WE HIGH to Low Z
[6]
33ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and capacitance C
L
= 30 pF.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. t
HZOE
, t
HZCE
, t
HZWE
are specified with C
L
= 5 pF as in AC Test Loads. Transition is measured ±500 mV from steady state voltage.
8. The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. The minimum write cycle time for write cycle #3 (WE
controlled, OE LOW) is the sum of t
HZWE
and t
SD
.