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CY7C1410JV18, CY7C1425JV18
CY7C1412JV18, CY7C1414JV18
Document #: 001-12561 Rev. *D Page 3 of 26
Logic Block Diagram (CY7C1412JV18)
Logic Block Diagram (CY7C1414JV18)
1M x 18 Array
CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
D
[17:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
20
36
18
BWS
[1:0]
V
REF
Write Add. Decode
Write
Reg
18
A
(19:0)
20
CQ
CQ
DOFF
Q
[17:0]
18
18
18
Write
Reg
C
C
1M x 18 Array
512K x 36 Array
CLK
A
(18:0)
Gen.
K
K
Control
Logic
Address
Register
D
[35:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
19
72
36
BWS
[3:0]
V
REF
Write Add. Decode
Write
Reg
36
A
(18:0)
19
CQ
CQ
DOFF
Q
[35:0]
36
36
36
Write
Reg
C
C
512K x 36 Array
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