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CY7C1410AV18, CY7C1425AV18
CY7C1412AV18, CY7C1414AV18
Document #: 38-05615 Rev. *E Page 2 of 29
Logic Block Diagram (CY7C1410AV18)
Logic Block Diagram (CY7C1425AV18)
2M x 8 Array
CLK
A
(20:0)
Gen.
K
K
Control
Logic
Address
Register
D
[7:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
8
21
16
8
NWS
[1:0]
V
REF
Write Add. Decode
Write
Reg
8
A
(20:0)
21
CQ
CQ
DOFF
Q
[7:0]
8
8
Write
Reg
C
C
2M x 8 Array
8
2M x 9 Array
CLK
A
(20:0)
Gen.
K
K
Control
Logic
Address
Register
D
[8:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
9
21
18
9
BWS
[0]
V
REF
Write Add. Decode
Write
Reg
9
A
(20:0)
21
CQ
CQ
DOFF
Q
[8:0]
9
9
Write
Reg
C
C
2M x 9 Array
9
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