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CY7C145, CY7C144
Document #: 38-06034 Rev. *D Page 13 of 21
Figure 16. Interrupt Timing Diagrams
Notes
30.t
HA
depends on which enable pin (CE
L
or R/W
L
) is deasserted first.
31.t
INS
or t
INR
depends on which enable pin (CE
L
or R/W
L
) is asserted last.
Switching Waveforms (continued)
WRITE 1FFF
t
WC
t
HA
Left Side Sets INT
R
:
ADDRESS
L
R/W
L
CE
L
INT
R
t
INS
[30]
[31]
Right Side Clears INT
R
:
READ 1FFF
t
RC
t
INR
WRITE 1FFE
t
WC
Right Side Sets INT
L
:
Left Side Clears INT
L
:
READ 1FFE
t
INR
t
RC
ADDRESS
R
CE
L
R/W
L
INT
L
OE
L
ADDRESS
R
R/W
R
CE
R
INT
L
ADDRESS
R
CE
R
R/W
R
INT
R
OE
R
t
HA
t
INS
[31]
[30]
[31]
[31]
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