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CY7C1470BV25
CY7C1472BV25, CY7C1474BV25
Document #: 001-15032 Rev. *D Page 9 of 29
access (read, write, or deselect) is latched into the Address
Register (provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ
and DQP
(DQ
a,b,c,d
/DQP
a,b,c,d
for CY7C1470BV25, DQ
a,b
/DQP
a,b
for
CY7C1472BV25, DQ
a,b,c,d,e,f,g,h
/DQP
a,b,c,d,e,f,g,h
for
CY7C1474BV25) (or a subset for Byte Write operations, see
“Partial Write Cycle Description” on page 11 for details) inputs is
latched into the device and the Write is complete.
The data written during the Write operation is controlled by BW
(BW
a,b,c,d
for CY7C1470BV25, BW
a,b
for CY7C1472BV25, and
BW
a,b,c,d,e,f,g,h
for CY7C1474BV25) signals. The
CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25
provides Byte Write capability that is described in “Partial Write
Cycle Description” on page 11. Asserting the WE
input with the
selected BW
input selectively writes to only the desired bytes.
Bytes not selected during a Byte Write operation remain
unaltered. A synchronous self-timed write mechanism has been
provided to simplify the write operations. Byte Write capability
has been included to greatly simplify read, modify, or write
sequences, which can be reduced to simple Byte Write opera-
tions.
Because the CY7C1470BV25, CY7C1472BV25, and
CY7C1474BV25 are common IO devices, data must not be
driven into the device while the outputs are active. OE
can be
deasserted HIGH before presenting data to the DQ
and DQP
(DQ
a,b,c,d
/DQP
a,b,c,d
for CY7C1470BV25, DQ
a,b
/DQP
a,b
for
CY7C1472BV25, and DQ
a,b,c,d,e,f,g,h
/DQP
a,b,c,d,e,f,g,h
for
CY7C1474BV25) inputs. Doing so tri-states the output drivers.
As a safety precaution, DQ
and DQP (DQ
a,b,c,d
/DQP
a,b,c,d
for
CY7C1470BV25, DQ
a,b
/DQP
a,b
for CY7C1472BV25, and
DQ
a,b,c,d,e,f,g,h
/DQP
a,b,c,d,e,f,g,h
for CY7C1474BV25) are
automatically tri-stated during the data portion of a write cycle,
regardless of the state of OE.
Burst Write Accesses
The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25
has an on-chip burst counter that enables the user to supply a
single address and conduct up to four write operations without
reasserting the address inputs. ADV/LD
must be driven LOW to
load the initial address, as described in “Single Write Accesses”
on page 8. When ADV/LD is driven HIGH on the subsequent
clock rise, the Chip Enables (CE
1
, CE
2
, and CE
3
) and WE inputs
are ignored and the burst counter is incremented. The correct
BW
(BW
a,b,c,d
for CY7C1470BV25, BW
a,b
for CY7C1472BV25,
and BW
a,b,c,d,e,f,g,h
for CY7C1474BV25) inputs must be driven
in each cycle of the burst write to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected before entering the “sleep” mode. CE
1
, CE
2
,
and CE
3
, must remain inactive for the duration of t
ZZREC
after the
ZZ input returns LOW.
Table 2. Linear Burst Address Table (MODE = GND)
First
Address
Second
Address
Third
Address
Fourth
Address
A1,A0 A1,A0 A1,A0 A1,A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Table 3. Interleaved Burst Address Table
(MODE = Floating or V
DD
)
First
Address
Second
Address
Third
Address
Fourth
Address
A1,A0 A1,A0 A1,A0 A1,A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min Max Unit
I
DDZZ
Sleep mode standby current ZZ > V
DD
− 0.2V 120 mA
t
ZZS
Device operation to ZZ ZZ > V
DD
− 0.2V 2t
CYC
ns
t
ZZREC
ZZ recovery time ZZ < 0.2V 2t
CYC
ns
t
ZZI
ZZ active to sleep current This parameter is sampled 2t
CYC
ns
t
RZZI
ZZ Inactive to exit sleep current This parameter is sampled 0 ns
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