Cypress CY7C150 Computer Hardware User Manual

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CY7C150

Document #: 38-05024 Rev. ** Page 3 of 11

Switching Characteristics Over the Operating Range

[2,5]

Parameter Description

7C150−10 7C150−12 7C150−15 7C150−25 7C150−35

UnitMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.

READ CYCLE

Read Cycle Time 10 12 15 25 35 ns

Address to Data Valid 10 12 15 25 35 ns

OHA

Output Hold from Address

Change

2 2 2 2 2 ns

ACS

CS LOW to Data Valid 8 10 12 15 20 ns

LZCS

CS LOW to Low Z

[6]

0 0 0 0 0 ns

HZCS

CS HIGH to High Z

[6,7]

6 8 11 20 25 ns

DOE

OE LOW to Data Valid 6 8 10 15 20 ns

LZOE

OE LOW to Low Z

[6]

0 0 0 0 0 ns

HZOE

OE HIGH to High Z

[6,7]

6 8 9 20 25 ns

WRITE CYCLE

[8]

Write Cycle Time 10 12 15 25 35 ns

SCS

CS LOW to Write End 6 8 11 15 20 ns

Address Set-Up to Write End 8 10 13 20 30 ns

Address Hold from Write End 2 2 2 5 5 ns

Address Set-Up to Write Start 2 2 2 5 5 ns

PWE

WE Pulse Width 6 8 11 15 20 ns

Data Set-Up to Write End 6 8 11 15 20 ns

Data Hold from Write End 2 2 2 5 5 ns

LZWE

WE HIGH to Low Z

[6]

0 0 0 0 0 ns

HZWE

WE LOW to High Z

[6,7]

6 8 12 20 25 ns

RESET CYCLE

RRC

Reset Cycle Time 20 24 30 50 70 ns

SAR

Address Valid to Beginning of

Reset

0 0 0 0 0 ns

SWER

Write Enable HIGH to Beginning

of Reset

0 0 0 0 0 ns

SCSR

Chip Select LOW to Beginning of

Reset

0 0 0 0 0 ns

PRS

Reset Pulse Width 10 12 15 20 30 ns

HCSR

Chip Select Hold After End of

Reset

0 0 0 0 0 ns

HWER

Write Enable Hold After End of

Reset

8 12 15 30 40 ns

HAR

Address Hold After End of Reset 10 12 15 30 40 ns

LZRS

Reset HIGH to Output in Low Z

[6]

0 0 0 0 0 ns

HZRS

Reset LOW to Output in

High Z

[6,7]

6 8 12 20 25 ns

Notes:

5. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified

and 30-pF load capacitance.

6. At any given temperature and voltage condition, t

is less than t

for any given device.

7. t

HZCS

, t

HZOE

, t

HZR

, and t

HZWE

are tested with C

= 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.

8. The internal write time of the memory is defined by the overlap of CS

LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate

a write by going HIGH. The data input set-up and hold timing should be reference to the rising edge of the signal that terminates the write.

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Cypress CY7C150 Computer Hardware User Manual