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CY7C1510JV18, CY7C1525JV18
CY7C1512JV18, CY7C1514JV18
Document #: 001-14435 Rev. *C Page 2 of 26
Logic Block Diagram (CY7C1510JV18)
Logic Block Diagram (CY7C1525JV18)
4M x 8 Array
CLK
A
(21:0)
Gen.
K
K
Control
Logic
Address
Register
D
[7:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
8
22
16
8
NWS
[1:0]
V
REF
Write Add. Decode
Write
Reg
8
A
(21:0)
22
CQ
CQ
DOFF
Q
[7:0]
8
8
8
Write
Reg
C
C
4M x 8 Array
2M x 9 Array
CLK
A
(20:0)
Gen.
K
K
Control
Logic
Address
Register
D
[8:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
9
21
18
9
BWS
[0]
V
REF
Write Add. Decode
Write
Reg
9
A
(20:0)
21
CQ
CQ
DOFF
Q
[8:0]
9
9
9
Write
Reg
C
C
2M x 9 Array
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