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CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
Document Number: 001-06550 Rev. *E Page 2 of 28
Logic Block Diagram (CY7C1546V18)
Logic Block Diagram (CY7C1557V18)
CLK
A
(21:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. Decode
Read Data Reg.
R/W
DQ
[7:0]
Output
Logic
Reg.
Reg.
Reg.
8
8
16
8
NWS
[1:0]
V
REF
Write Add. Decode
8
8
LD
Control
22
4M x 8 Array
4M x 8 Array
Write
Reg
Write
Reg
CQ
CQ
R/W
DOFF
QVLD
8
CLK
A
(21:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. Decode
Read Data Reg.
R/W
DQ
[8:0]
Output
Logic
Reg.
Reg.
Reg.
9
9
18
9
BWS
[0]
V
REF
Write Add. Decode
9
9
LD
Control
22
4M x 9 Array
4M x 9 Array
Write
Reg
Write
Reg
CQ
CQ
R/W
DOFF
QVLD
9
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