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CY8C20x36/46/66, CY8C20396
Document Number: 001-12696 Rev. *D Page 11 of 34
32-Pin QFN
Table 5. Pin Definitions - CY8C20436/46/66 PSoC Device
[2, 3]
Pin
No.
Type
Name Description
Figure 5. CY8C20436/46/66 PSoC Device
Digital Analog
1 IOH I P0[1] Integrating input
2 IO I P2[7]
3 IO I P2[5] Crystal output (XOut)
4 IO I P2[3] Crystal input (XIn)
5 IO I P2[1]
6 IO I P3[3]
7 IO I P3[1]
8 IOHR I P1[7] I2C SCL, SPI SS
9 IOHR I P1[5] I2C SDA, SPI MISO
10 IOHR I P1[3] SPI CLK.
11 IOHR I P1[1] ISSP CLK
[1]
, I2C SCL, SPI MOSI.
12 Power Vss Ground connection.
13 IOHR I P1[0] ISSP DATA
[1]
, I2C SDA., SPI CLK
14 IOHR I P1[2]
15 IOHR I P1[4] Optional external clock input
(EXTCLK)
16 IOHR I P1[6]
17 Input XRES Active high external reset with
internal pull down
18 IO I P3[0]
19 IO I P3[2]
20 IO I P2[0]
21 IO I P2[2]
22 IO I P2[4]
23 IO I P2[6]
24 IOH I P0[0]
25 IOH I P0[2]
26 IOH I P0[4]
27 IOH I P0[6]
28 Power Vdd Supply voltage
29 IOH I P0[7]
30 IOH I P0[5]
31 IOH I P0[3] Integrating input
32 Power Vss Ground connection
CP Power Vss Center pad must be connected to
ground
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
AI, P0[1]
AI, P2[7]
AI, XOut, P2[5]
AI, XIn, P2[3]
AI, P2[1]
AI, P3[3]
QFN
(Top View)
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
Vss
P0[3], AI
P0[7], AI
Vdd
P0[6], AI
P0[4], AI
P0[2], AI
AI, P3[1]
AI, I2C SCL, SPI SS, P1[7]
P0[0], AI
P2[6], AI
P3[0], AI
XRES
AI, I2C SDA, SPI MISO, P1[5]
AI,SPICLK,P1[3]
Vss
AI, P1[2]
AI, EXTCLK, P1[4]
AI, P1[6]
P2[4], AI
P2[2], AI
P2[0], AI
P3[2], AI
P0[5], AI
AI, CLK
4
, I2C SCL, SPI MOSI, P1[1]
AI, DATA
1
, I2C SDA, SPI CLK, P1[0]
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