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STK14D88
Document Number: 001-52037 Rev. ** Page 10 of 17
Mode Selection
E W G A
14
–A
0
Mode IO Power Notes
H X X X Not Selected Output High Z Standby
L H L X Read SRAM Output Data Active
L L X X Write SRAM Input Data Active
L H L 0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x03F8
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Disable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active 18, 19, 20
L H L 0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x07F0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active 18, 19, 20
L H L 0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Active
18, 19, 20
0x0FC0 Nonvolatile Store Output High Z I
CC2
L H L 0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active 18, 19, 20
Notes
18.The six consecutive addresses must be in the order listed. W
must be high during all six consecutive cycles to enable a nonvolatile cycle.
19.While there are 15 addresses on the STK14D88, only the lower 14 are used to control software modes
20.I/O state depends on the state of G
. The I/O table shown assumes G low.
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