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STK15C88
Document Number: 001-50593 Rev. ** Page 11 of 15
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows.
[11, 12]
Parameter Alt Description
25 ns 45 ns
Unit
Min Max Min Max
t
RC
t
AVAV
STORE/RECALL Initiation Cycle Time 25 45 ns
t
SA
[11]
t
AVEL
Address Setup Time 0 0 ns
t
CW
[11]
t
ELEH
Clock Pulse Width 20 30 ns
t
HACE
[7, 11]
t
ELAX
Address Hold Time 20 20 ns
t
RECALL
RECALL Duration 20 20 μs
Switching Waveforms
Figure 10. CE Controlled Software STORE/RECALL Cycle
[12]
t
RC
t
RC
t
SA
t
SCE
t
HACE
t
STORE
/ t
RECALL
DATA VALID
DATA VALID
6#SSERDDA1#SSERDDA
HIGH IMPEDANCE
ADDRESS
CE
OE
DQ (DATA)
Notes
11. The software sequence is clocked on the falling edge of CE
without involving OE (double clocking will abort the sequence).
12.The six consecutive addresses must be read in the order listed in the Mode Selection table. WE
must be HIGH during all six consecutive cycles.
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