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STK16C88
Document Number: 001-50595 Rev. ** Page 8 of 14
AC Switching Characteristics
Table 3. SRAM Read Cycle
Parameter
Description
25 ns 45 ns
Unit
Min Max Min Max
Cypress
Parameter
Alt
t
ACE
t
ELQV
Chip Enable Access Time 25 45 ns
t
RC
[5]
t
AVAV,
t
ELEH
Read Cycle Time 25 45 ns
t
AA
[6]
t
AVQV
Address Access Time 25 45 ns
t
DOE
t
GLQV
Output Enable to Data Valid 10 20 ns
t
OHA
[6]
t
AXQX
Output Hold After Address Change 5 5 ns
t
LZCE
[7]
t
ELQX
Chip Enable to Output Active 5 5 ns
t
HZCE
[7]
t
EHQZ
Chip Disable to Output Inactive 10 15 ns
t
LZOE
[7]
t
GLQX
Output Enable to Output Active 0 0 ns
t
HZOE
[7]
t
GHQZ
Output Disable to Output Inactive 10 15 ns
t
PU
[4]
t
ELICCH
Chip Enable to Power Active 0 0 ns
t
PD
[4]
t
EHICCL
Chip Disable to Power Standby 25 45 ns
Switching Waveforms
Figure 5. SRAM Read Cycle 1: Address Controlled
[5, 6]
Figure 6. SRAM Read Cycle 2: CE and OE Controlled
[5]
W
5&
W
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W
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W
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W
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W
+=&(
2(
W
'2(
W
/=2(
W
+=2(
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W
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Notes
5. WE
must be HIGH during SRAM Read Cycles and LOW during SRAM WRITE cycles.
6. I/O state assumes CE
and OE < V
IL
and WE > V
IH
; device is continuously selected.
7. Measured ±200 mV from steady state output voltage.
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