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DS_IPM24S0
7
B0_03202007
TEST CONFIGURATIONS
V
I
(+)
V
I
(-)
BATTERY
2
100uF
Electrolytic
L
TO OSCILLOSCOPE
Ceramic
3.3uF
Note: Input reflected-ripple current is measured with a
simulated source inductance. Current is
measured at the input of the module.
Figure 23: Input reflected-ripple current test setup
Vo
GND
COPPER STRIP
220uF
PosCap
1uF
ceramic
SCOPE
Resistive
Load
Note: Use a 220µF PosCap and 1µF capacitor. Scope
measurement should be made using a BNC
connector.
Figure 24: Peak-peak output noise and startup transient
measurement test setup
SUPPLY
I
I
V
I
Vo
GND
Io
LOAD
CONTACT AND
DISTRIBUTION LOSSES
CONTACT RESISTANCE
Figure 25: Output voltage and efficiency measurement test
setup
Note: All measurements are taken at the module
terminals. When the module is not soldered (via
socket), place Kelvin connections at module
terminals to avoid measurement errors due to
contact resistance.
%100)( ×
×
×
=
IiVi
IoVo
η
DESIGN CONSIDERATIONS
Input Source Impedance
To maintain low-noise and ripple at the input voltage, it is
critical to use low ESR capacitors at the input to the
module. Figure 26 shows the input ripple voltage
(mVp-p) for various output models using 2x100uF low
ESR electrolytic capacitors (Rubycon P/N:50YXG100,
100uF/50V or equivalent) and 1x3.3.0 uF very low ESR
ceramic capacitors (TDK P/N: C4532JB1H335M,
3.3uF/50V or equivalent).
The input capacitance should be able to handle an AC
ripple current of at least:
Arms
Vin
Vout
Vin
Vout
IoutIrms
⎟
⎠
⎞
⎜
⎝
⎛
−= 1
Figure 26: Input ripple voltage for various output models,
Io = 3A (Cin =2x100uF electrolytic capacitors
1x3.3uF ceramic capacitors at the input)
The power module should be connected to a low
ac-impedance input source. Highly inductive source
impedances can affect the stability of the module. An
input capacitance must be placed close to the modules
input pins to filter ripple current and ensure module
stability in the presence of inductive traces that supply
the input voltage to the module.