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C141-E106-01EN 5 - 17
Note:
1. When the L bit is specified to 1, the lower 4 bits of the DH register and all bits of the
CH, CL and SN registers indicate the LBA bits (bits of the DH register are the MSB
(most significant bit) and bits of the SN register are the LSB (least significant bit).
2. At error occurrence, the SC register indicates the remaining sector count of data transfer.
3. In the table indicating I/O registers contents in this subsection, bit indication is omitted.
(1) READ SECTOR(S) (X'20' or X'21')
This command reads data of sectors specified in the Sector Count register from the address specified in
the Device/Head, Cylinder High, Cylinder Low and Sector Number registers. Number of sectors can be
specified to 256 sectors in maximum. To specify 256 sectors reading, '00' is specified. For the DRQ,
INTRQ, and BSY protocols related to data transfer, see Subsection 5.4.1.
If the head is not on the track specified by the host, the device performs an implied seek. After the
head reaches to the specified track, the device reads the target sector.
The DRQ bit of the Status register is always set prior to the data transfer regardless of an error
condition.
Upon the completion of the command execution, command block registers contain the cylinder,
head, and sector addresses (in the CHS mode) or logical block address (in the LBA mode) of the
last sector read.
If an error occurs in a sector, the read operation is terminated at the sector where the error occurred.
Command block registers contain the cylinder, the head, and the sector addresses of the sector (in
the CHS mode) or the logical block address (in the LBA mode) where the error occurred, and
remaining number of sectors of which data was not transferred.
At command issuance (I/O registers setting contents)
1F7
H
(CM)0010000R
1F6
H
(DH)
×
L
×
DV Start head No. /LBA [MSB]
1F5
H
(CH)
1F4
H
(CL)
1F3
H
(SN)
1F2
H
(SC)
1F1
H
(FR)
Start cylinder No. [MSB]/ LBA
Start cylinder No. [LSB]/ LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx
R = 0 or 1