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8 SPARC Enterprise T5120 and T5220 Servers Overview Guide • July 2009
Additional Feature Information
■ “Chip-Multithreaded Processor and Memory Technology” on page 8
■ “Performance Enhancements” on page 9
■ “Preinstalled Solaris Operating System” on page 9
■ “Hardware-Assisted Cryptography” on page 10
■ “Support for Virtualization Through Logical Domains (LDoms)” on page 10
■ “Remote Manageability With ILOM” on page 11
■ “High Levels of System Reliability, Availability, and Serviceability” on page 12
■ “Fault Management and Predictive Self Healing” on page 16
■ “Rackmountable Enclosure” on page 16
Chip-Multithreaded Processor and Memory
Technology
The UltraSPARC T2 multicore processor is the basis of the SPARC Enterprise T5120
and T5220 servers. The UltraSPARC T2 processor is based on chip multithreading
(CMT) technology that is optimized for highly threaded transactional processing. The
UltraSPARC T2 processor improves throughput while using less power and
dissipating less heat than conventional processor designs.
Depending on the model purchased, the processor has four, six, or eight UltraSPARC
cores. Each core equates to a 64-bit execution pipeline capable of running eight
threads. The result is that the 8-core processor handles up to 64 active threads
concurrently.
Additional processor components, such as L1 cache, L2 cache, memory access
crossbar, memory controllers, and the I/O interface have been carefully tuned for
optimal performance.
Related Information
■ SPARC Enterprise T5120 and T5220 Servers Product Notes
■ SPARC Enterprise T5120 and T5220 Servers Installation Guide
■ SPARC Enterprise T5120 and T5220 Servers Administration Guide
■ SPARC Enterprise T5120 and T5220 Servers Service Manual