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GR160 F1 specifications
Dual processor configuration guide
NOTE: Quad Rank DIMMs and Unbuffered DIMMs can only use a maximum of 6 slots per CPU (12 slots
total)
DIMM CPU 1 CPU 2
# 1B 1A 2B 2A 3B 3A 1B 1A 2B 2A 3B 3A
2 X X
3 X X X
4 X X X X
6 X X X X X X
8 X X X X X X X X
9 X X X X X X X X X
12 X X X X X X X X X X X X
* support depends on 8GB DIMM available
Mirroring mode:
• For mirroring mode, the memory contains a primary image and a copy of the primary image. Therefore,
the effective size of memory is reduced by at least one-half.
• Follow the population rules described in independent mode.
• Mirroring mode needs the channel 1 & channel 2 with identical DIMM. DIMM slot populations within a
channel do not have to be identical but the same DIMM slot location across channel 1 and channel 2
must be the same. DIMM1A and DIMM2A should be the same type, size and manufacturer. DIMM1B
and DIMM2B memory should be the same type, size and manufacturer. DIMM1C and DIMM2C
memory should be the same type, size and manufacturer.
• Same rule is applied to the CPU2.
• Please refer to the User Guide for complete population for both single and dual processor
configurations.
Lockstep mode:
• In Lockstep Channel Mode, each memory access is a 128-bit data access that spans Channel 1 and
Channel 2. This is done to support SDDC for DRAM devices with 8-bit wide data ports. The same
address is used on both channels such that an address error on any channel is detectable by bad
ECC. Lockstep Channel mode is the only RAS mode that supports x8 SDDC.
• Follow the population rules described in independent mode.
• Lockstep mode needs the channel 1 & channel 2 with identical DIMM. DIMM slot populations within a
channel do not have to be identical but the same DIMM slot location across channel 1 and channel 2
must be the same. DIMM1A and DIMM2A should be the same type, size and manufacturer. DIMM1B
and DIMM2B memory should be the same type, size and manufacturer. DIMM1C and DIMM2C
memory should be the same type, size and manufacturer.
• Same rule is applied to the CPU2.
• Please refer to the User Guide for complete population for both single and dual processor
configurations.