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6.0 Electrostatic Discharge Precautions
The following discussion applies mainly to GaAs FET devices, but
excess voltages can damage a silicon bipolar device as well. Slight
degradation of a GaAs FET device can occur with electrostatic
potentials as low as 500 volts and capacitances on the order of that of
the human body. Unfortunately, it is very easy to generate static charge
of this magnitude through the motion of an arm, by sliding plastic
objects together, or by the motion of the body on a chair cushion.
Static discharges that we can feel or hear are on the order of 10 kV by
comparison.
Any time a potential difference can be applied between the elements of
a transistor, damage can result. Therefore, in chip form, prior to
bonding, the transistor is relatively immune to damage. Once the
bonding has been started though, caution must be exercised to prevent
device damage. HP uses the following procedures for E.S.D. preven-
tion in assembly areas, and recommends their use.
1. Operators use wrist straps connected to earth ground through 1
megohm resistors (for operator safety).
2. All equipment is grounded to earth ground including heater blocks,
bonders, and test equipment.
3. Work surfaces are covered with anti-static mats (not metal) which
are grounded to earth ground.
4. All operators wear anti-static smocks made of material which is
woven with 1% stainless steel wire.
5. Floors and seat cushions are treated periodically with an anti-static
solution.
6. A periodic survey of work areas is conducted with a static potential
meter to monitor potential build-ups or grounding failures.
Part II. Design Considerations
1.0 RF Performance Considerations
1.1 General
In general, optimum chip transistor performance is obtained with the
shortest possible bond wire lengths. This puts obvious constraints on
circuit layout and chip positioning. Most designers using FETs
minimize gate and source bond lengths at the expense of longer drain
bond wires. Thermocompression-wedge bonding yields the shortest
bond wire length for a given pad separation because the bond comes
off the pad in a more horizontal direction.
1.2 Hewlett-Packard Chip Device Characterization
HP GaAs FET chip transistors are characterized on a standard chip
carrier which consists of 50 ohm alumina microstrip lines (of 0.100
inch length and 0.025 inch thickness) on either side of a metal bar
(0.030 inch long) upon which the FET chip is mounted. The transistor
is centered on the bar and bond wires for input (gate) and output
(drain) are of equal length. Minimum bond lengths for the sources are