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Technical Reference Guide www.hp.com 3-1
3
Processor/Memory Subsystem
3.1 Introduction
This chapter describes the processor/memory subsystem. This systems support the AMD
Phenom, Athlon, and Sempron processor families. As shown in Figure 3-1, these processors use
an integrated DDR2 memory controller and communicate with the chipset through the
HyperTranport interface (I/F).
Figure 3-1. Processor/Memory Subsystem Architecture
This chapter includes the following topics:
■ AMD processors (3.2)
■ Memory subsystem (3.3)
Controller
DDR2
XMM1
Channel A
DIMM
DIMM
DIMM
DIMM
XMM2
XMM4
XMM3
AMD Processor
Channel B
Core(s)
L2 Cache
HyperTransport I/F
North Bridge