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As with the z990, an improvement to the I/O subsystem
has been introduced on the z890 to “break the barrier”
of the 256 CHPIDs per Channel Subsystem. Horizontal
growth is provided by allowing the defi nition of two Logical
Channel SubSystems (LCSSs) each capable of supporting
up to 256 CHPIDs, giving a total of 512 CHPIDs per z890
server. The z890 can support up to 30 Logical Partitions
(LPARs). There is still a 256 CHPID limit per operating
system. (Note: The lowest Capacity Setting 110 can sup-
port up to 240 CHPIDs, dependent on channel type, and
up to a maximum of 15 LPARs.)
These are some of the signifi cant enhancements in the
zSeries 890 server that bring improved performance, avail-
ability and function to the platform. The following sections
highlight the functions and features of the server.
z890 Design and Technology
The z890 is designed to provide balanced system perfor-
mance. From server to the storage to the system’s I/O and
network channels, end-to-end bandwidth is provided and
designed to deliver data where and when it is needed. The
z890 is a scaled down version of the z990 using one of
the most advanced chip and packaging technology in the
industry. The z890 has more technology similarities to the
z990 than the z800 does to the z900. Both the z890 and
z990 use the latest MCM packaging and book package.
The z890 compared to the z800 provides a signifi cant
increase in system scalability and opportunity for server
consolidation by providing improved model granularity
while scaling to 2X the performance of the z800. The
z890’s processor cycle time has been improved to 1.0 ns
from the 1.6 ns of the z800. All z890’s have a single Mul-
tiChip Module (MCM) that is nearly identical to the z990’s
MultiChip module. The differences are minor. With fewer
functional processors and a slower cycle time less power
is required for the z890 MCM enabling air cooling. The
air cooled z890 MCM uses approximately 450 Watts
compared to the liquid cooled z990 MCM which requires
approximately 650 Watts. The z890 MCM can deliver 1 to
4-way confi gurations with a variety of engine sizes. The
z890 MCM, which measures approximately 95 x 95 mil-
limeters, is about 42% smaller than the z900’s 127 mm
x 127 mm MCM. The z890 MCM contains 5 Processor
Unit (PU) chips, four Storage Data (Level 2 cache) chips,
a Level 2 Cache Storage Controller chip and two main
Memory Storage Controller (MSC) chips which control the
main memory or Level 3 storage. The MCM contains 101
glass ceramic layers of which 23 layers are to provide
interconnection between the chips and the off-module
environment. In total, there are approximately 378 meters
of internal copper wiring on both the z890 and z990 MCMs
compared to the 997 meters of internal wiring needed
for the MCMs in the z900 190 and 290 models. The new
smaller MCM packaging delivers an MCM with many
shorter paths. The z890 MCM is 40% smaller than the
z900 MCM. It has over 20% more I/O connections and
over a 130% I/O density improvement compared to the
z900 MCM.
The z890’s MCM provides support for 5 PUs and 32 MB
level 2 cache which can be shared by all PUs. Each PU
chip contains approximately 122 million transistors and
measures 14.1 mm x 18.9 mm. The design of the MCM
technology on the z890 provides the fl exibility to confi g-
ure the PUs for different uses. One of the PUs is reserved
for use as dedicated I/O Processor (IOP), commonly
referred to as a System Assist Processor (SAP) enabling
the Central Processor to avoid the burden of I/O set