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Specification Update 21
HSD14. Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value
for VEX.vvvv May Produce a #NM Exception
Problem: The VAESIMC and VAESKEYGENASSIST instructions should produce a #UD (Invalid-
Opcode) exception if the value of the vvvv field in the VEX prefix is not 1111b. Due to
this erratum, if CR0.TS is “1”, the processor may instead produce a #NM (Device-Not-
Available) exception.
Implication: Due to this erratum, some undefined instruction encodings may produce a #NM instead
of a #UD exception.
Workaround: Software should always set the vvvv field of the VEX prefix to 1111b for instances of
the VAESIMC and VAESKEYGENASSIST instructions.
Status: For the steppings affected, see the Summary Table of Changes.
HSD15. Processor May Fail to Acknowledge a TLP Request
Problem: When a PCIe root port’s receiver is in Receiver L0s power state and the port initiates a
Recovery event, it will issue Training Sets to the link partner. The link partner will
respond by initiating an L0s exit sequence. Prior to transmitting its own Training Sets,
the link partner may transmit a TLP (Transaction Layer Packet) request. Due to this
erratum, the root port may not acknowledge the TLP request.
Implication: After completing the Recovery event, the PCIe link partner will replay the TLP request.
The link partner may set a Correctable Error status bit, which has no functional effect.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
HSD16. Interrupt From Local APIC Timer May Not Be Detectable While Being
Delivered
Problem: If the local-APIC timer’s CCR (current-count register) is 0, software should be able to
determine whether a previously generated timer interrupt is being delivered by first
reading the delivery-status bit in the LVT timer register and then reading the bit in the
IRR (interrupt-request register) corresponding to the vector in the LVT timer register. If
both values are read as 0, no timer interrupt should be in the process of being
delivered. Due to this erratum, a timer interrupt may be delivered even if the CCR is 0
and the LVT and IRR bits are read as 0. This can occur only if the DCR (Divide
Configuration Register) is greater than or equal to 4. The erratum does not occur if
software writes zero to the Initial Count Register before reading the LVT and IRR bits.
Implication: Software that relies on reads of the LVT and IRR bits to determine whether a timer
interrupt is being delivered may not operate properly.
Workaround: Software that uses the local-APIC timer must be prepared to handle the timer
interrupts, even those that would not be expected based on reading CCR and the LVT
and IRR bits; alternatively, software can avoid the problem by writing zero to the Initial
Count Register before reading the LVT and IRR bits.
Status: For the steppings affected, see the Summary Table of Changes.