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Specification Update 29
HSD44. Display May Flicker When Package C-States Are Enabled
Problem: When package C-States are enabled, the display may not be refreshed at the correct
rate.
Implication: When this erratum occurs, the user may observe flickering on the display.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
HSD45. Certain Combinations of AVX Instructions May Cause Unpredictable
System Behavior
Problem: Execution of certain combinations of AVX instructions may lead to unpredictable system
behavior.
Implication: When this erratum occurs, unpredictable system behaviors, including system hang or
incorrect results can occur.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
HSD46. Processor May Incorrectly Estimate Peak Power Delivery
Requirements
Problem: Under certain conditions, the processor may incorrectly calculate the frequency at
which the cores and graphics engine can operate while still meeting voltage regulator
and power supply peak power delivery capabilities. When this occurs, combined with
high power workloads, system shutdown may be observed.
Implication: When this erratum occurs, system shutdown may be observed under high power
workloads.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
HSD47. IA32_PERF_CTL MSR is Incorrectly Reset
Problem: The IA32_PERF_CTL MSR (199H) is not initialized correctly after a processor reset.
Implication: If software reads the IA32_PERF_CTL MSR before writing it, software can observe an
incorrect reset value. Although incorrect values are reported to software, the correct
default values for this register are still used by the processor. No performance or power
impact occurs due to this erratum.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
HSD48. Processor May Hang During a Function Level Reset of the Display
Problem: When package C-States are enabled, it is possible that the processor may hang when
software performs a Function Level Reset of the display via bit 1 of the Advanced
Features Control Register (Bus 0; Device 2; Function 0; Offset 0A8H).
Implication: When this erratum occurs, the processor may hang.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.