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Specification Update 23
HSD21. PCIe Root Port May Not Initiate Link Speed Change
Problem: The PCIe Base specification requires the upstream component to maintain the PCIe link at the
target link speed or the highest speed supported by both components on the link, whichever is
lower. PCIe root port will not initiate the link speed change without being triggered by the software
when the root port maximum link speed is configured to be 5.0 GT/s. System BIOS will trigger
the link speed change under normal boot scenarios. However, BIOS is not involved in
some scenarios such as link disable/re-enable or secondary bus reset and therefore the
speed change may not occur unless initiated by the downstream component. This
erratum does not affect the ability of the downstream component to initiate a link
speed change. All known 5.0Gb/s-capable PCIe downstream components have been
observed to initiate the link speed change without relying on the root port to do so.
Implication: Due to this erratum, the PCIe root port may not initiate a link speed change during
some hardware scenarios causing the PCIe link to operate at a lower than expected
speed. Intel has not observed this erratum with any commercially available platform.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
HSD22. Pending x87 FPU Exceptions (#MF) May be Signaled Earlier Than
Expected
Problem: x87 instructions that trigger #MF normally service interrupts before the #MF. Due to
this erratum, if an instruction that triggers #MF is executed while Enhanced Intel
SpeedStep
®
Technology transitions, Intel
®
Turbo Boost Technology transitions, or
Thermal Monitor events occur, the pending #MF may be signaled before pending
interrupts are serviced.
Implication: Software may observe #MF being signaled before pending interrupts are serviced.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
HSD23. DR6.B0-B3 May Not Report All Breakpoints Matched When a MOV/POP
SS is Followed by a Store or an MMX Instruction
Problem: Normally, data breakpoints matches that occur on a MOV SS, r/m or POP SS will not
cause a debug exception immediately after MOV/POP SS but will be delayed until the
instruction boundary following the next instruction is reached. After the debug
exception occurs, DR6.B0-B3 bits will contain information about data breakpoints
matched during the MOV/POP SS as well as breakpoints detected by the following
instruction. Due to this erratum, DR6.B0-B3 bits may not contain information about
data breakpoints matched during the MOV/POP SS when the following instruction is
either an MMX instruction that uses a memory addressing mode with an index or a
store instruction.
Implication: When this erratum occurs, DR6 may not contain information about all breakpoints
matched. This erratum will not be observed under the recommended usage of the MOV
SS,r/m or POP SS instructions (i.e., following them only with an instruction that writes
(E/R)SP).
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.