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Specification Update 33
HSD62. Some Performance Monitor Event Counts May be Inaccurate During
SMT Mode
Problem: The performance monitor event OFFCORE_REQUESTS_OUTSTANDING (Event 60H, any
Umask Value) should count the number of occurrences that loads or stores stay in the
super queue each cycle. The performance monitor event
CYCLE_ACTIVITY.CYCLES_L2_PENDING (Event A3H, Umask 01H) should count the
number of cycles that demand loads stay in the super queue. However, due to this
erratum, these events may count inaccurately during SMT mode.
Implication: The performance monitor events OFFCORE_REQUESTS_OUTSTANDING and
CYCLE_ACTIVITY.L2_ PENDING may be unreliable during SMT Mode.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
HSD63. Timed MWAIT May Use Deadline of a Previous Execution
Problem: A timed MWAIT instruction specifies a TSC deadline for execution resumption. If a wake
event causes execution to resume before the deadline is reached, a subsequent timed
MWAIT instruction may incorrectly use the deadline of the previous timed MWAIT when
that previous deadline is earlier than the new one.
Implication: A timed MWAIT may end earlier than expected.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
HSD64. The Upper 32 Bits of CR3 May be Incorrectly Used With 32-Bit Paging
Problem: When 32-bit paging is in use, the processor should use a page directory located at the
32-bit physical address specified in bits 31:12 of CR3; the upper 32 bits of CR3 should
be ignored. Due to this erratum, the processor will use a page directory located at the
64-bit physical address specified in bits 63:12 of CR3.
Implication: The processor may use an unexpected page directory or, if EPT (Extended Page Tables)
is in use, cause an unexpected EPT violation. This erratum applies only if software
enters 64-bit mode, loads CR3 with a 64-bit value, and then returns to 32-bit paging
without changing CR3. Intel has not observed this erratum with any commercially
available software.
Workaround: Software that has executed in 64-bit mode should reload CR3 with a 32-bit value
before returning to 32-bit paging.
Status: For the steppings affected, see the Summary Table of Changes.
HSD65. Performance Monitor Events HLE_RETIRED.ABORTED_MISC4 And
RTM_RETIRED.ABORTED_MISC4 May Over Count
Problem: The Performance Monitor Events HLE_RETIRED.ABORTED_MISC4 (Event C8H; Umask
40H) and RTM_RETIRED.ABORTED_MISC4 (Event C9H; Umask 40H) are defined to
count the number of transactional aborts due to incompatible memory types. Due to
this erratum, they may count additional unrelated transactional aborts.
Implication: The Performance Monitor Events HLE_RETIRED.ABORTED_MISC4 and
RTM_RETIRED.ABORTED_MISC4 counts may be greater than the number of aborts due
to incompatible memory types.
This can result in nonzero counts when all memory
types are compatible.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.