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Specification Update 35
HSD70. IA32_VMX_VMCS_ENUM MSR (48AH) Does Not Properly Report The
Highest Index Value Used For VMCS Encoding
Problem: IA32_VMX_VMCS_ENUM MSR (48AH) bits 9:1 report the highest index value used for
any VMCS encoding. Due to this erratum, the value 21 is returned in bits 9:1 although
there is a VMCS field whose encoding uses the index value 23.
Implication: Software that uses the value reported in IA32_VMX_VMCS_ENUM[9:1] to read and
write all VMCS fields may omit one field.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
HSD71. Incorrect FROM_IP Value For an RTM Abort in BTM or BTS May be
Observed
Problem: During RTM (Restricted Transactional Memory) operation when branch tracing is
enabled using BTM (Branch Trace Message) or BTS (Branch Trace Store), the incorrect
EIP value (From_IP pointer) may be observed for an RTM abort.
Implication: Due to this erratum, the From_IP pointer may be the same as that of the immediately
preceding taken branch.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
HSD72. VT-d Hardware May Perform STRP And SIRTP Operations on a Package
C7 Exit
Problem: On a package C7 exit, VT-d hardware may spuriously perform SRTP (Set Root Table
Pointer) and SIRTP (Set Interrupt Remapping Table Pointer) operations. A package C7
exit can cause the value programmed by software in the RTA_REG (IRTA_REG) to be
visible to hardware before software executes a GCMD.SRTP command. This will result in
hardware using the new values for the DMA and interrupt translation page-walks,
possibly before they are intended to be used by software.
Implication: If software has updated the root table pointer but has not executed the SRTP command
then the root table pointer update will happen unexpectedly, causing the VMM to walk
incorrect or non-existent tables. Intel has not observed this erratum with any
commercially available software.
Workaround: Privileged software should not execute a MWAIT (because it can trigger a package C7
entry/exit) between writing to RTA_REG (IRTA_REG) and GCMD_REG.SRTP
(GCMD_REG.SIRTP) registers.
Status: For the steppings affected, see the Summary Table of Changes.
HSD73. General-Purpose Performance Counters Can Unexpectedly Increment
Problem: A performance monitor event programmed in a general-purpose performance counter
should count the number of occurrences of the event selected in IA32_PERFEVTSEL{0-
7} MSR (186H-18DH).
If INV (invert, bit 23) is set to 1 and a non-zero CMASK
(Counter Mask) bits [31:24] value is used, due to this erratum, the event may over
count in the case that either of OS (Operating System mode, bit 17) or USR (User
mode, bit 16) is selected. Over counting will occur for the cycles spent in the non-
matching CPL.
Implication: General-purpose performance counters may reflect counts higher than the actual
number of events when the INV bit is set, CMASK is a non-zero value and either the OS
or USR bit is set.
Workaround: None identified.