Intel D845PESV Computer Hardware User Manual


 
Desktop Board Features
11
Main Memory
NOTE
To be fully compliant with all applicable Intel
®
SDRAM memory specifications, the board should
be populated with DIMMs that support the Serial Presence Detect (SPD) data structure. If your
memory modules do not support SPD, you will see a notification to this effect on the screen at
power up. The BIOS will attempt to configure the memory controller for normal operation.
Desktop Board D845PESV supports system memory as defined below:
Up to two 184-pin Double Data Rate (DDR) SDRAM Dual Inline Memory Modules (DIMMs)
with gold-plated contacts. Supported memory configuration are:
DDR333: to run DDR333 memory at full speed requires an Intel Pentium 4 processor with
533 MHz front side bus frequency (FSB)
DDR333 memory will run only at DDR266 speeds when using a processor with 400 MHz
FSB
DDR266: requires an Intel Pentium 4 processor with
533/400 MHz FSB, or Intel Celeron processor with 400 MHz FSB
DDR200: requires an Intel Pentium 4 or Intel Celeron processor with 400 MHz FSB
Unbuffered and non-registered single or double-sided DIMMs
Serial Presence Detect (SPD) memory only
Non-ECC RAM (ECC memory will run in non-ECC mode)
2.5 V memory
64 Mbit, 128 Mbit, 256 Mbit, and 512 Mbit technologies for the following memory
configurations:
64 MB (minimum)
256 MB (64 Mbit technology)
512 MB (128 Mbit technology)
1024 MB (256 Mbit technology)
2048 MB (512 Mbit technology)
NOTE
Desktop Board D845PESV has been designed to support DIMMs based on 512 Mbit technology up
to 2 GB, but this technology has not been validated on this Intel desktop board. For more
information about the latest list of tested memory, refer to the Intel World Wide Web site at:
http://support.intel.com/support/motherboards/desktop/
All memory components and DIMMs used with the desktop board must comply with the
PC SDRAM specifications. You can access these documents through the World Wide Web at:
http://www.intel.com/technology/memory/pcsdram/spec/
For information about installing memory, see Chapter 2 starting on page 21.